1. Field of the Invention
The present invention relates to a device for electrostatic discharge protection (hereinafter, referred to as “ESD”), and more specifically, to an ESD device in which an oxide film is formed on a boundary of a drain drift region and a drain active region to implement an OLI_GG_DDDNMOS device, whereby the current concentrated on the surface of the device can be uniformly distributed over the entire device.
2. Discussion of Related Art
In manufacturing semiconductor a chip that operates at high voltage, the role of a device for ESD protection, which protects the chip from electrostatic, is very important.
One of the basic characteristics that a semiconductor device operating at high voltage must have is that a junction breakdown voltage must be higher than an operating voltage. In order to satisfy this characteristic, a N-type MOSFET adopting the drain in which a dopant is diffused twice, as shown in FIG. 1, so-called Double Diffused Drain N-type MOSFET (DDDNMOS) is used as a basic element.
FIGS. 1a and 1b are cross-sectional views of conventional unidirectional and bidirectional DDDNMOS devices.
Referring to FIG. 1a, a plurality of field oxide films 102 are formed in predetermined regions on a P-type semiconductor substrate 101. A gate 103 is formed over the semiconductor substrate 101 between the field oxide films 102. A well pick-up region 104 is formed on the semiconductor substrate 101 between the field oxide film 102 and the field oxide film 102 by means of a high concentration P-type impurity ion implant process. A source active region 105 is formed on the semiconductor substrate 101 between the field oxide film 102 and the gate 103 by means of a high concentration N-type impurity ion implant process. Furthermore, a drain is formed between the gate 103 and the field oxide films 102 by performing a dual N-type impurity ion implant process. The drain region has a drain active region 107 of a high concentration formed within the drain drift region 106 of a low concentration.
Generally, the lower the impurity concentrations of two regions, which are in contact with each other with an electrically opposite polarity, the higher the junction breakdown voltage. Accordingly, the drain in which a dopant is diffused in dual is formed by means of the method as shown. In this state, if the impurity concentration of the drift region, which is in contact with a P-well region having an electrically opposite polarity, is lowered, a desired junction breakdown voltage can be implemented.
A DDDNMOS device can be classified into two kinds depending on its formation method; a structure in which a dopant is diffused into only the drain twice, as shown in FIG. 1a, i.e., an unidirectional DDDNMOS device, and a structure in which a dopant is diffused into both the drain and the source, as shown in FIG. 1b, i.e., a bidirectional DDDNMOS device. The junction breakdown voltages of the two structures are almost the same.
The structure of the bidirectional DDDNMOS device will be describe with reference to FIG. 1b. A plurality of field oxide films 202 are formed in predetermined regions on a P-type semiconductor substrate 201. A gate 203 is formed over the semiconductor substrate 201 between the field oxide films 202. A well pick-up region 204 is formed on the semiconductor substrate 201 between the field oxide film 202 and the field oxide film 202 by means of a P-type impurity ion implant process. A source is formed on the semiconductor substrate 201 between the field oxide film 202 and the gate 203 by means of a dual N-type impurity ion implant process. A source active region 206 of a high concentration is formed within a source drift region 205 of a low concentration. Furthermore, a drain is formed between the gate 203 and the field oxide films 202 by means of a dual N-type impurity ion implant process. In this time, a drain active region 208 of a high concentration is formed within a drain drift region 207 of a low concentration.
FIGS. 2a and 2b are views illustrating electrode connection modes of GG_DDDNMOS devices in which the conventional unidirectional and bidirectional DDDNMOS devices are used as devices for electrostatic discharge protection.
In order for a DDDNMOS device operating at high voltage to be used as a device for ESD protection, an electrode is constructed in such a manner that the gate, the source and the well pick-up region are bundled and grounded, and a positive voltage is applied to the drain, as shown in FIGS. 2a and 2b. In the GG_DDDNMOS (Gate Grounded DDDNMOS) having the electrode constructed above, if a voltage applied to the drain is lower than an operating voltage, current rarely flows since the gate and source, and a channel (region under the gate where a current path is formed) keeps almost the same electrical potential.
On the contrary, if the voltage applied to the drain is higher than the junction breakdown voltage, an impact ionization phenomenon occurs at the boundary where the semiconductor substrate and the drain drift region meet, and a plurality of carriers are thus formed. As a result, a parasitic NPN-BJT (NPN Bipolar Junction Transistor) is formed, and a large amount of current thus flows between the drain and the source. Consequently, in the GG_DDDNMOS having the electrode constructed above, the current does not flow at a voltage lower than the operating voltage, but the current smoothly flows at a voltage higher than the operating voltage. Accordingly, the GG_DDDNMOS can be used as a device for ESD protection, which digests undesired stress current in an electrostatic discharge situation to protect internal circuits.
FIGS. 3a and 3b show multi-finger structures of conventional unidirectional and bidirectional GG_DDDNMOS devices.
In order to secure the capability of coping with a large amount of stress current when GG_DDDNMOS is used as a device for ESD protection, a multi-finger GG_DDDNMOS as shown in FIGS. 3a and 3b is used.
FIGS. 4a and 4b are views illustrating the current paths of the conventional unidirectional and bidirectional GG_DDDNMOS devices.
FIGS. 5a and 5b are views illustrating thermal breakdown points of the conventional unidirectional and bidirectional GG_DDDNMOS devices.
FIGS. 4a, 4b, 5a and 5b show a conductive path along which current flows when a GG_DDDNMOS operates as a device for ESD protection.
If a parasitic NPN-BJT is formed in the GG_DDDNMOS and a high current starts to flow, low resistive current paths are formed over the drain, the channel and the source. Current paths A and B have a characteristic that they are limited to a restricted region along the surface of the device. If the current paths A and B are limitedly formed along the surface of the device and current is concentrated on that portion, a temperature of the surface of the device sharply rises and a thermal breakdown phenomenon is thus generated on the surface. The phenomenon that the current is concentrated on the surface and the thermal breakdown phenomenon accordingly serve as a factor to degrade the capability of a GG_DDDNMOS to cope with ESD stress current. After a result of confirming a location where the thermal breakdown phenomenon is generated as the stress current rises when GG_DDDNMOS operates as a device for ESD protection through simulation, it was found that the thermal breakdown phenomenon is generated because a temperature sharply rises in a very limited region of the surface of the device at a boundary C of the drain active region 106 and the drain drift region 107, as shown in FIGS. 5a and 5b. 
Accordingly, in order to improve the capability of a GG_DDDNMOS to cope with ESD stress current when the GG_DDDNMOS is used as the device for ESD protection of the semiconductor chip that operates at high voltage, there is a need for a method in which concentration of the current on the surface of the device is mitigated so that the current is uniformly distributed over the device.